1. Field of the Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for accelerating the transfer of data in a computer system utilizing multiple buses.
2. History of the Prior Art
Historically, personal computers have utilized a single bus to transfer data between different internal components of the system. In personal computers using central processing units designed and manufactured by Intel Corporation of Santa Clara, Calif., such buses have typically been designed as either an Industry Standard Association (ISA) bus or an Expanded Industry Standard Association (EISA) bus. The ISA bus is a sixteen bit data bus while the EISA bus is thirty-two bits wide. These bus widths and the rates at which each of these buses is capable of operating have been found limiting so there have been a number of attempts to increase bus speed.
One recently implemented method of increasing bus speed is to provide an additional, so called, "local bus" which is more closely associated with the central processor than either of the above-mentioned buses and which is capable of running at speeds that more closely approximate the speed at which the processor itself runs. Those system components which require faster operation than has been available using the slower buses (such as an output display card for an output display device) are joined to this faster local bus. The slower ISA or EISA bus is continued in essentially unchanged form, and those components which are able to tolerate longer access times are associated with the slower bus. Although the theory behind using a local bus is good, many local bus designs have created conflicts in accessing components which actually slowing the operation of the computer.
Intel Corporation has designed a new local bus which may be associated in a computer system including an Intel processor with other buses such as an ISA bus or an EISA bus (which are hereinafter referred to broadly as secondary buses). This new local bus provides faster throughput of data for selected components of the system without the conflicts which arise using other local bus systems. This new bus is referred to as the "peripheral component interconnect" (PCI) bus. A computer system using this PCI bus includes in addition to the physical PCI bus a first bridge circuit which controls the transfer of data among the PCI bus, the central processing unit, and main memory. A second bridge circuit is also arranged to control the transfer of data between the secondary bus and the PCI bus. Thus, the arrangement is such that components on the PCI bus transfer data to and receive data from main memory through the first bridge which joins to the central processor and to the main memory; while components on the secondary bus transfer and receive data through the second bridge and through the PCI bus for transfers with components on the PCI bus, and through the second and first bridges and the PCI bus for transfers with the central processor and the main memory.
Various designs of secondary bridges have been proposed. One design specifically utilized to transfer data and addresses between the PCI bus and an ISA bus is referred to as an SIO bridge. Such a bridge is described in detail in a publication entitled 82420/82430 PCIset, ISA and EISA Bridges, 1993, Intel Corporation. One of the problems of this and other bridge circuits is that since the transfer must go in both directions between the buses, the circuitry for accomplishing the transfer often becomes quite complicated. Thus, it has been found to be very difficult to provide data rapidly without a substantial number of clock delays between the two buses connected by the secondary bridge.